RID-GRASP: Redundancy Identification and Removal Using GRASP

Redundancy identification and removal is a critical step that typically follows logic synthesis or optimization. In principle, it should be possible to restrict the transformations applied by synthesis and optimization algorithms to those that preserve testability. In practice, however, few, if any, synthesis programs can guarantee the irredundancy of the logic circuits they produce. It may also be argued that identifying and removing redundancy as a post-processing step affords synthesis tools greater flexibility in restructuring the logic. This paper presents RID-GRASP, an ATPG-based redundancy identification and removal system. Unlike structural analysis-based redundancy removal algorithms, ATPG-based systems can guarantee 100-percent redundancy removal assuming there is no aborted fault. But the downfall of this approach is that it can show its worst case behavior for redundant faults. GRASP, a new search algorithm for boolean satisfiability is known to show good performance in proving unsatisfiability. GRASP is used to prove the redundancy of a logic element in our redundancy removal system. The most notable feature of RID-GRASP is that it can implicitly remove a redundancy in a logic circuit by simply setting a constraint in the CNF (conjunctive normal form) representation of the circuit without changing the circuit structure.